1. Field of the Invention
The present invention relates to a semiconductor device having a buried element isolation region by burying an insulator in a micropatterned groove formed in a semiconductor substrate and a method of manufacturing the same.
2. Description of the Related Art
In order to form a large number of semiconductor elements in a semiconductor substrate so as to isolate them from each other, the following method is known. That is, an insulator is buried in a micropatterned groove formed in the semiconductor substrate to form an element isolation region, and semiconductor elements are formed in the semiconductor regions isolated by the element isolation region. For example, a method of manufacturing a semiconductor device in which an insulator is buried in a groove to form an element isolation region is disclosed in U.S. Pat. No. 4,532,696. In the semiconductor device disclosed in the U.S. Pat. No. 4,532,696, the surface of a semiconductor substrate is covered with an insulating film, and semiconductor regions isolated by an element isolation region are connected by an aluminum wire through a contact hole formed in the insulating film.
There is, however, a semiconductor device in which two adjacent semiconductor regions are directly connected with each other to form a conductive layer along the substrate surface without formation of a contact hole. In this case, a step is formed in a portion of the groove on which an element isolation region is formed, and the conductive layer formed on this step may be disconnected.
A conventional method of manufacturing a semiconductor device will be described below with reference to FIGS. 1A to 1K.
As shown in FIG. 1A, a mask material 13 (SiN.sub.3, SiO.sub.2, or the like) is deposited on an oxide film 12 of a semiconductor substrate 11. As shown in FIG. 1B, a resist film 14 having a groove pattern 15 is formed by a photoresist method. As shown in FIG. 1C, anisotropic etching such as RIE (Reactive Ion Etching) is performed for the groove pattern 15 using the resist film 14 as a mask to continuously etch the mask material 13, the oxide film 12, and the semiconductor substrate 11 so as to form a groove 16 corresponding to the groove pattern 15.
As shown in FIG. 1D, after the resist film 14 is removed, an insulating film 17 is deposited in the groove 16 represented by a broken line and on the entire surface of the substrate 11 by a CVD method, and the insulating film 17 is anisotropically etched and left in the groove 16. The residual insulating film 17 is etched back by an etchant 18 such that the upper surface of the insulating film 17 is located between the upper and lower surfaces of the mask material 13.
As shown in FIG. 1E, the mask material 13 is removed to project the upper surface of the insulating film 17 from the upper surface of the oxide film 12.
A gate electrode material is deposited on the entire surface of the resultant structure, and a resist film (not shown) is formed by a photoresist method. Thereafter, anisotropic etching is performed using the resist film as a mask, and the resist film is removed after this etching. As shown in FIG. 1F, a gate electrode 19 is formed.
In the semiconductor device with the above arrangement, poor step coverage 20 of the gate electrode 19 occurs in the step portion between the buried insulating film 17 and the oxide film 12 to degrade the conductivity of the semiconductor device.
In the above manufacturing method, the mask material 13 is used. The second conventional manufacturing method without using the mask material will be described below.
As shown in FIG. 1G, an oxide film 12 is formed on a semiconductor substrate 11.
As shown in FIG. 1H, a resist film 14 having a groove pattern 15 is formed by a photoresist method on an oxide film 12.
As shown in FIG. 1I, the oxide film 12 and the semiconductor substrate 11 are continuously and anisotropically etched by an etchant 21 using the resist film 14 as a mask to form a groove 16.
As shown in FIG. 1J, after the resist film 14 is removed, an insulating film 17 is deposited in the groove 16 and on the entire surface of the substrate using a CVD method, and the insulating film 17 is anisotropically etched back. The residual insulating film 17 is etched such that the upper surface of the insulating film 17 is lower than the upper surface of the oxide film 12.
A gate electrode material is deposited on the entire surface of the substrate 11, and a resist film (not shown) is formed by a photoresist method. Thereafter, anisotropic etching is performed using the resist film as a mask, and the resist film is removed after this etching. As shown in FIG. 1K, a gate electrode 22 is formed.
In the semiconductor substrate with the above arrangement, when over-etching is performed during formation of the gate electrode 22, the semiconductor substrate 11 under the insulating film 12 is adversely affected. Therefore, this over-etching cannot be performed. For this reason, an etching residue 22' of the gate electrode material is formed on the groove 16. The etching residue is formed between a plurality of semiconductor devices formed in a direction perpendicular to the drawing surface, thereby causing electrical short-circuiting.
Even if either conventional method is used in the corresponding conventional semiconductor device, the semiconductor substrate surface is roughened, and poor step coverage of a wiring and short-circuiting caused by an etching residue of a wiring material occur.
As described above, in the conventional semiconductor device, poor step coverage of the wiring occurs due to unevenness of the semiconductor substrate surface and buried insulating film surface, and degradation of conductivity of the semiconductor device and shortcircuiting occur.